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Product Descriptions

Pin/Code Compatible with all 80960Jx Processors

High-Performance Embedded Architecture

— One Instruction/Clock Execution

— Core Clock Rate is:

80960JA/JF 1x the Bus Clock

80960JD 2x the Bus Clock

80960JT 3x the Bus Clock

— Load/Store Programming Model

— Sixteen 32-Bit Global Registers

— Sixteen 32-Bit Local Registers(8 sets)

— Nine Addressing Modes

— User/Supervisor Protection Model

Two-Way Set Associative Instruction Cache

— 80960JA -2 Kbyte

— 80960JF/JD -4 Kbyte

— 80960JT -16 Kbyte

— Programmable Cache Locking Mechanism

Direct Mapped Data Cache

— 80960JA-1 Kbyte

— 80960JF/D-2 Kbyte

— 80960JT -4 Kbyte

— Write Through Operation

On-Chip Stack Frame Cache

— Seven Register Sets Can Be Saved

— Automatic Allocation on Call/Return

— 0-7 Frames Reserved for High-Priority Interrupts

Actual product photos

Product Data Manual：

For more product information, please download the PDF

Payment&Transportation

Official Certificate&Certificate

Multiple product supply

Company office environment

Warehouse Real Shot

Standard packaging

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