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Product Descriptions

The XMOS XS1-L01A-TQ128 is a powerful device that provides a simple design process and highly-flexible solution to many applications. The device consists of a single xCORE Tile, which comprises a flexible multicore microcontroller with tightly integrated I/O and on-chip memory. The processor runs mutiple tasks simultaneously using logical cores, each of which is guaranteed a slice of processing power and can execute computational code, control software and I/O interfaces. Logical cores use channels to exchange data within a tile or across tiles. Multiple devices can be deployed and connected using an integrated switching network, enabling more resources to be added to a design. The I/O pins are driven using intelligent ports that can serialize data, interpret strobe signals and wait for scheduled times or events, making the device ideal for real-time control applications. 

The device can be configured using a set of software components that are rapidly customized and composed. XMOS provides source code libraries for many standard components. The device can be programmed using high-level languages such as C/C++ and XMOS-originated extensions to C, called XC, that simplify the control over concurrency, I/O and time. 

The XMOS toolchain includes compilers, a simulator, debugger and static timing analyzer. The combination of real-time software, a compiler and timing analyzer enables the programmer to close timings on components of the design without a detailed understanding of the hardware characteristics.

Product Features

· Single-Tile Multicore Microcontroller with Advanced Multi-Core RISC Architecture 

? Up to 500 MIPS shared between up to 8 real-time logical cores 

? Each logical core has: 

— Guaranteed throughput of between 1/4 and 1/8 of tile MIPS 

— 16x32bit dedicated registers 

? 159 high-density 16/32-bit instructions 

— All have single clock-cycle execution (except for divide)

— 32x32→64-bit MAC instructions for DSP, arithmetic and user-definable cryptographic functions

· Programmable I/O 

? 64 general-purpose I/O pins, configurable as input or output

? Port sampling rates of up to 60 MHz with respect to an external clock 

? 32 channel ends for communication with other cores, on or off-chip

· Memory 

? 64KB internal single-cycle SRAM for code and data storage

? 8KB internal OTP for application boot code

· JTAG Module for On-Chip Debug · Security Features

? Programming lock disables debug and prevents read-back of memory contents

? AES bootloader ensures secrecy of IP held on external flash memory

· Ambient Temperature Range 

? Commercial qualification: 0 °C to 70 °C 

? Industrial qualification: -40 °C to 85 °C

· Speed Grade

? 5: 500 MIPS

? 4: 400 MIPS

· Power Consumption

? Active Mode 

— 200 mA at 500 MHz (typical) 

— 160 mA at 400 MHz (typical) 

? Standby Mode

— 14 mA 

? Sleep Mode 

— Programmable PCU module puts device into sleep mode 

— Wakeup on external signal or timeout

· 128-pin TQFP package 0.4 mm pitch

Actual product photos

Product Data Manual：

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