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Product Descriptions

RK3026/RK3028Ais a low power, high performance processor solution for tablet, Android Portable GPS and other digital multimedia applications, and integrates Dual-core Cortex-A9 with separatelyNeon and FPU coprocessor ,and also with256KB L2 Cache.

Many embedded powerful hardware engines provide optimized performance for high-end application. RK3026/RK3028A supports almost full-format video decoder by 1080p@60fps, also support H.264/MVC/VP8 encoder by 1080p@30fps, high-quality JPEG encoder/decoder and special image preprocessor and postprocessor .

Embedded 3D GPU makes RK3026/RK3028A completely compatible with OpenGL ES1.1 and 2.0, OpenVG1.1 etc. Special 2D hardware engine with MMU will maximize display performance.

RK3026/RK3028A has high-performance external memory interface(DDR3/LVDDR3) capable of sustaining demanding memory bandwidths, also

provides a complete set of peripheral interface to support very flexible applications as follows :

This document will provide guideline on how to use RK3028A correctly and efficiently. In them , the chapter 1 and chapter 2 will introduce the features, block diagram, signal descriptions and system usage of RK3028A, the chapter 3 through chapter 5 will describe the function,electricalcharacteristics and hardware guideline.

Product Features

1.2.1 MicroProcessor

•  Dual-core ARM Cortex-A9 processor is a high-performance, low-power, cached application processor

•  Full implementation of the ARM architecture v7-A instruction set, ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation

•  Superscalar, variable length, out-of-order pipeline with dynamic branch prediction, 8-stage pipeline

•  Include VFPv3 hardware to support single and double-precision add, subtract, divide, multiply and accumulate, and square root operations

•  Integrated timer and watchdog timer in CPU

•  Integrated 32KB L1 instruction cache , 32KB L1 data cache, 4-way set associative

•  256KB unified L2 Cache

•  coresight debug solution

•  Invasive debug

•  One isolated voltage domain to support DVFS

1.2.2 Memory Organization

•  Internal on-chip memory

•  16KBBootRom

•  8KB internal SRAM

•  External off-chip memory①

•  DDR3-1600, 16bits data width, 2 ranks, 256MB(max) address space per rank

•  LVDDR3-1600, 16bits data width, 2 ranks, 256MB(max) address space per rank

•  Async/ Sync Toggle/Sync ONFI Nand Flash(include LBA Nand), 8bits data width,4 banks
  

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