Product Details
| Features ? PC100-compliant ? Fully synchronous; all signals registered on positive edge of system clock ? Internal pipelined operation; column address can be changed every clock cycle ? Internal banks for hiding row access/precharge ? Programmable burst lengths: 1, 2, 4, 8, or full page ? Auto precharge, includes concurrent auto precharge and auto refresh modes ? Self refresh mode (not available on AT devices) ? Auto refresh – 64ms, 4096-cycle refresh (commercial and industrial) – 16ms, 4096-cycle refresh (automotive) ? LVTTL-compatible inputs and outputs ? Single 3.3V ±0.3V power supply ? Supports CAS latency (CL) of 1, 2, and 3 |
Product Description
| TYPE | DESCRIPTION |
| ANSC PART# | ANSC - MT48LC4M32B2P-6A IT:L |
| Category | Integrated Circuits (ICs) |
| Memory | |
| Memory | |
| Mfr | Original |
| Series | - |
| Packaging | Bulk |
| Part Status | Obsolete |
| DigiKey Programmable | Not Verified |
| Memory Type | Volatile |
| Memory Format | DRAM |
| Technology | SDRAM |
| Memory Size | 128Mbit |
| Memory Organization | 4M x 32 |
| Memory Interface | Parallel |
| Clock Frequency | 167 MHz |
| Write Cycle Time - Word, Page | 12ns |
| Access Time | 5.4 ns |
| Voltage - Supply | 3V ~ 3.6V |
| Operating Temperature | -40°C ~ 85°C (TA) |
| Mounting Type | Surface Mount |
| Package / Case | 86-TFSOP (0.400", 10.16mm Width) |
| Supplier Device Package | 86-TSOP II |
| Base Product Number | MT48LC4M32B2 |
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Product datasheet
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