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Product Details

GL850G-60 is Genesys Logic’s advanced STT hub solutions which fully comply with Universal Serial Bus Specification Revision 2.0. GL850G-60 inherits Genesys Logic’s cutting edge technology on cost and power efficient serial interface design. GL850G-60 has proven compatibility, lower power consumption figure and better cost structure above all USB2.0 hub solutions worldwide.

GL850G-60 provides multiple advantages to simplify board level design that help achieving lowest BOM (Bill of Material) for system integrator. GL850G-60 integrates both 5V to 3.3V and 3.3V to 1.8V low dropout voltage regulator into single chip, therefore no external LDO required.

GL850G-60 embeds an 8-bit RISC processor to manipulate the control/status registers and respond to the requests from USB host. Firmware of GL850G-60 will control its general purpose I/O (GPIO) to access the external EEPROM and then respond to the host the customized PID and VID configured in the external EEPROM. Default settings in the internal mask ROM is responded to the host without having external EEPROM. GL850G-60 provides better design flexibility for customers. The complicated settings such as PID, VID, and number of downstream ports settings…etc. are easily achieved by programming the external EEPROM or SMBUS mode.

GL850G-60 is a full function solution which supports both Individual and Gang (4 ports as a group) mode for power management (Individual mode is only available in QFN28 package). Number of downstream ports and non/removable downstream port can be configured by different ways, such as EEPROM, SMBUS or I/O strapping. For the detailed configuration methods, please refer to the following table.

Products Features

* Compliant to USB Specification Revision 2.0

   * Upstream port supports both high-speed (HS) and full-speed (FS) traffic
   * Downstream ports support HS, FS, and low-speed (LS) traffic
   * 1 control pipe (endpoint 0, 64-byte data payload) and 1 interrupt pipe (endpoint1, 1-byte data payload)
   * Backward compatible to USB specification Revision 1.1
 
* On-chip 8-bit micro-processor

   * RISC-like architecture
   * USB optimized instruction set
   * Performance: 6 MIPS @ 12MHz
   * With 64-byte RAM and 4K mask ROM
   * Support customized PID, VID by external EEPROM/ SMBUS/
   * Support downstream port configuration by external EEPROM/ SMBUS/
 
* Single Transaction Translator (STT)

   * Single TT shares the same TT control logics for all downstream port devices. This is the most cost effective solution for TT.
 
* Integrate USB 2.0 transceiver

* Improve output drivers with slew-rate control for EMI reduction

   * Internal power-fail detection for ESD recovery
 
* Low BOM cost

* Built-in 5V to 3.3V regulator

   * Built-in upstream 1.5KΩ pull high and downstream 15KΩ pull-down
   * Built-in PLL supports external 12 MHz crystal / Oscillator clock input
   * Embed serial resister for USB signals
 
* Low power support

   * Support Selective Suspend
   * Support LPM L1 with EEPROM
 
* Smart power mode

   * Support both individual and gang modes of power management and over-current detection for downstream ports
     (Individual mode is not supported by SSOP 28 package)
   * Conform to bus power requirements
 
* Flexible design

   * Number of Downstream port can be configured by SMBUS / EEPROM/
   * Compound-device (non-removable in downstream ports) could be configured by I/O strapping/ SMBUS / EEPROM/
   * Automatic switching between self-powered and bus-powered modes
 
* Available package:

   * 28 pin QFN (5x5mm)
   * 28 pin SSOP (209mil)
   * 24 pin QFN (4x4mm)
 
* Applications:

   * Standalone USB hub
   * NB / Tablet / Motherboard / Docking Station
   * Gaming console
   * LCD monitor hub
   * Any compound device to support USB hub function

Specifications

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